The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low resistance and capacitance interconnect properties, particularly where submicron inter-layer interconnects and intra-layer interconnects have increasingly high aspect ratios and densities.
In the fabrication of semiconductor devices, increased device density requires multiple layers, making necessary the provision of a multi-layered interconnect structure. Such a multi-layered interconnect structure typically includes intra-layer conductive interconnects and inter-layer conductive interconnects, formed by anisotropically etched openings in dielectric insulating layers, often referred to as an inter-metal dielectric (IMD) layer, and subsequently filling the openings with metal, for example copper. Commonly used inter-layer high aspect ratio openings are commonly referred to as vias, for example, when the opening extends through an insulating layer between two conductive layers. The intra-layer interconnects extend horizontally in the IMD layer to interconnect different areas within an IMD layer and are often referred to as trench lines. In one manufacturing approach, trench lines are formed overlying and encompassing one or more vias to form metal inlaid interconnects referred to as dual damascene structures.
In a typical process for forming multiple layer interconnect structure, for example, in a via-first dual damascene process, via openings are first anisotropically etched through an IMD layer by conventional photolithographic and etching techniques. A second anisotropically etched opening, referred to as a trench opening, is then formed according to a second photolithographic patterning process overlying and encompassing one or more of the via openings. The via openings and the trench opening together makeup the dual damascene structure which is subsequently filled with metal, for example, copper, followed by a CMP planarization process to planarize the wafer process surface and prepare the process surface for formation of another overlying level in a multi-level semiconductor device.
In particular, the undesirable effects of integrated circuit RC delay and signal crosstalk increase as integrated circuit densities increase, requiring increasingly low dielectric constants to decrease the parasitic capacitances of the dielectric insulating layers. For example, in design rule technologies of less than about 0.25 microns including 0.1 microns and lower, dielectric insulating layers having a dielectric constant of less than about 2.5, also referred to as ultra low-K dielectrics, are required to achieve acceptable circuit densities with reliable electrical behavior. Silicon dioxide based dielectric layers doped with carbon or organic substituents and forming an interconnecting porous structure within the SiO2 matrix are increasingly desirable for forming IMD layers. Porous low-K materials have several drawbacks including enhanced absorption of chemical species which may easily migrate throughout the IMD layer.
One problem associated with absorption and migration of absorbed chemical species is photoresist poisoning, believed to be related to the interference of nitrogen species with chemically amplified deep ultraviolet (DUV) photoresists, typically used for 0.25 micron and below CMOS technology. Many DUV photoresists are chemically amplified using a photoacid generator activated by the light source to make an exposed area soluble in the development process. One problem affecting the anisotropicity of etching dual damascene features, particularly with respect to the trench portion etching process, is related to photoresist poisoning in the trench patterning process. For example, undeveloped photoresist residue from the trench patterning process frequently forms around the via opening prior to the trench etching process and tends to degrade etching profiles in both the trench portion and via portion of the completed dual damascene structure. The photoresist residue has been attributed to interference by residual nitrogen-containing containing species, for example amines, being released from the porous low-K materials in the patterning process after having been contaminated by a previous process, for example PECVD deposition of dielectrics such as hard masks, anti-reflective coatings, and etch stop layers.
Another problem with low-K materials including carbon doping or carbon-silicon substituents in a silicon dioxide matrix to form an IMD layer relates to the common practice of subjecting the trench patterning photoresist to a plasma ashing process following the trench etching process. The plasma ashing process has been found to damage the low-K material by depleting the carbon from the IMD layer and thereby increasing the dielectric constant of the IMD layer. Various approaches to solving processing problems with low-K dielectrics have been proposed. One approach includes partially or substantially filling the via with a photoresist material prior to trench etching. This approach has met with difficulties due to the formation of etching resistant polymeric residues around the via opening following the trench etching process. Another approach has been to use hard masks or liners for etching the trench to avoid damage to the low-K IMD layer during the photoresist ashing process. This approach has the drawback of leading to enlarged (faceted) trench openings due to etching process chemistries that are not sufficiently selective to the low-K material. Increasing the hard mask layer thickness to prevent trench opening faceting in the trench etching process has been found to have the undesirable effect of reducing surface planarity as well as requiring increased photoresist thickness over via portions in the trench pattering process thereby undesirably affecting patterning resolution.
There is therefore a need in the semiconductor processing art to develop a method to reliably pattern and etch dual damascene structures including avoiding photoresist poisoning and ashing damage to low-K materials to achieve improved device performance and reliability.
It is therefore an object of the invention to provide a method to reliably pattern and etch dual damascene structures including avoiding photoresist poisoning and ashing damage to low-K materials to achieve improved device performance and reliability while overcoming other shortcomings and deficiencies in the prior art.